1. Field of the Invention
The present invention generally relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a write area divided into a plurality of blocks so that written information can be protected from being rewritten on an individual block basis.
Recently, in association with unity with regard to a power source for non-volatile semiconductor memory devices, a demand for a function to prevent recorded information from being erroneously rewritten, that is, a write-protection function, has been increased.
2. Description of the Related Art
A conventional semiconductor device has a write area divided into a plurality of blocks, and written information in the write area is prevented from being rewritten. This function is referred to as a write-protection function. A setting operation of the write protection is performed on an individual block basis.
A description will now be given, with reference to FIG. 1, of a write-protection circuit provided in the conventional semiconductor device.
The write-protection circuit 201 shown in FIG. 1 comprises: a write-protection control circuit 212 which controls an operation for setting write-protection information; an input buffer circuit 23 which inputs an address signal for designating a block to be write-protected; a decode circuit 24 which decodes the address signal so as to designate the block to which the write-protection information is set; and a write-protection setting circuit 211 which performs the operation for setting the write-protection to the block designated by the operation of the write-protection control circuit 212.
The write-protection circuit 201 performs the write-protection setting operation based on the address signal and externally input control signals such as an output enable signal OE and a write enable signal WE. That is, when there is a plurality of blocks to be write-protected, a plurality of write-protection setting operations are performed for the blocks on an individual block basis.
It should be noted that the write-protection circuit 201 of the conventional semiconductor memory device uses an address signal A6 as a control signal for the write-protection setting operation. Additionally, the write-protection circuit 201 uses the uppermost address signals A14, A15 and A16 (represented as Ai in FIG. 1) as a signal for designating a block to which the write-protection setting operation is applied.
The write-protection setting circuit 211 includes, as shown in FIG. 2, write-protection memory circuits 221a through 221g each of which stores the write-protection information for a respective one of the blocks. The write protection is set by storing the write-protection information in each of the write-protection memory circuits 221a through 221g.
Additionally, the conventional semiconductor device turns on an N-channel transistor 33 by changing a signal PDC3 shown in FIG. 2 from 0 Vcc to 0.5 Vcc each time a data writing operation is performed so as to read a write-protection signal WP which corresponds to the write-protection information provided to the block to which the data write operation is applied. That is, the write-protection signal to be read is the write-protection information stored in one of the protection memory circuits 211a through 221g provided to one of the blocks to which the data write operation is to be performed. It should be noted that the write-protection information represents whether the write-protection for each of the blocks is set or canceled.
Specifically, the conventional semiconductor memory device recognizes that the block is write-protected when the write-protection signal WP is at a high level ("H"). On the other hand, when the write-protection signal WP is at a low level ("L"), it is recognized that the write-protection of the block has been canceled.
A description will now be given, with reference to FIG. 3, of a write-protection setting operation performed by the write-protection circuit 201.
When the address signal Ai (A14, A15, A16) is input to the input buffer circuit 23, the decode circuit 24 decodes the address signal Ai so as to designate one of the blocks to which the write-protection setting operation is applied. For example, when the block 0 is designated, a block signal BLK0 is set to the high level (FIG. 3-1).
FIG.4 is a circuit diagram of the write-protection control circuit 212 shown in FIG. 1. In the above-mentioned state, when the control signal OE/ is recognized by a high-voltage detecting circuit 41, and the effective address signal A6 and the control signal WE/ are input to a NAND gate 47 via input buffer circuits 42 and 43, respectively, the write-protection control circuit 212 outputs a write signal WPP and a control gate signal WPG via inverters 48 and 49, respectively.
Specifically, when the control signal OE=12V, the address signal A6="L", and the control signal WE="L", the write-protection control circuit 212 sets the write signal WPP and the control gate signal WPG to "H" (FIG. 3-2) so as to control the write-protection setting operation of the write-protection setting circuit 211.
When both the signals WPP and WPG are "H", the write-protection setting circuit 211 stores the write-protection information in one of the write-protection memory circuits 221a to 221g. In the present case, the write-protection information is stored in the protection memory circuit 221a which corresponds to the block 0 (the block signal BLK0). Each of the write-protection memory circuits 221a to 221g comprises, as shown in FIG. 5, a memory circuit which is a content addressable memory (CAM) cell 81, a P-channel transistor 82, an N-channel transistor 83 and a NAND gate 84. Each of the write-protection memory circuits 221a to 221g stores the protection information corresponding to the designated block based on the signals WPP and WPG.
As mentioned above, the conventional write-protection circuit 201 performs the write-protection setting operation with respect to the block 0 (BLK0), and thereafter sequentially performs the write-protection setting operation for other blocks (BLKn) one after another (FIG. 3-3, 4, 5, 6, 7, 8)
As mentioned above, the conventional semiconductor memory device must perform a plurality of write-protection setting operations when there are a plurality of blocks to be write-protected. Accordingly, there is a problem in that a relatively long time is required to set the write protection to all of the blocks to be write-protected. Specifically, a time for setting all of the blocks to be write-protected is calculated by multiplying a time (about 100 microseconds) needed to perform the write-protection setting operation for a single block by a number of blocks to be write-protected.